Design of 2.4 GHZ CMOS Frontend for Bluetooth

Diploma Thesis from the year 2001 in the subject Electrotechnology, grade: 1,0, Technical University of Munich (unbekannt), language: English, abstract: Inhaltsangabe:Abstract:§The Bluetooth wireless technology is the worlds new short-range RF transmission standard for small form factor, low-cost, short-range radio links between portable or desktop devices. The technology promises to eliminate the confusion of cables, connectors and protocols confounding communications between today high tech products.§In the first step a 2.45 GHz Low Noise Amplifier (LNA), intended for use in a Bluetooth receiver, has been designed in a standard 0.18 um CMOS process. The amplifier provides a simulated switchable forward voltage gain of +16 / -7.7 dB with a simulated noise Figure (NF) of only 3 dB while drawing 2.8 mA from a 1.8 V supply. The die area of the LNA (pads included) is 0.79 mm2.§In the second step a 2.45 GHz Power Amplifier (PA), also intended for the Bluetooth standard, has been designed in the same 0.18 um CMOS process as for the LNA. The class-A PA achieves a simulated forward gain (S21) of 23 dB and a simulated output 1 dB compression point (P1dB ) of 5.5 dBm, with a power-added efficiency (PAE) of 23 % while drawing 15.8 mA from a 1.8 V supply. The die area of the PA (pads included) is 2.1 mm2.§Inhaltsverzeichnis:Table of Contents:§1.Introduction1§1.1Motivation1§1.2Organization2§2.The Bluetooth standard3§2.1Bluetooth as branding-name3§2.2Bluetooth RF requirements4§2.3System design4§2.3.1Receiver architectures4§2.3.2Transmitter architectures6§3.RF CMOS technology9§3.1The foundry9§3.1.1Technology overview9§3.1.2Process Characteristic9§3.2Design Flow10§3.2.1Cadence10§3.2.2SpectreRF10§4.Integrated spiral inductors11§4.1View and physical dimension of spiral11§4.2Model for on-chip spiral inductors12§5.Low Noise Amplifier13§5.1Architecture choices13§5.1.1Recent studies13§5.1.2LNA Architectures13§5.1.3Architecture properties14§5.1.4Architecture choice14§5.2A little piece of theory15§5.2.1Standard MOS noise model15§5.2.2Noise Figure16§5.2.3Input impedance16§5.2.4Voltage Gain18§5.2.5Stability19§5.2.6Noise Figure20§5.3Design approach for the LNA21§5.3.1Circuit topology21§5.3.2RF circuit design strategy21§5.3.3DC operating point design strategy23§5.3.4Input matching24§5.3.5Voltage gain25§5.3.6Noise Figure26§5.3.7Stability27§5.3.8LNA core schematics with component values28§5.4Design approach for the attenuation path of the LNA29§5.4.1Circuit Topology29§5.4.2Switching network29§5.4.3Input matching31§5.4.4Attenuation32§5.4.5Switchable LNA schematics with component values33§5.5Summary of simulation33§5.6Layout34§5.7Measurement approach36§5.7.1Simulation results36§5.7.2Summary of simulation39§6.Power Amplifier41§6.1Architecture choices41§6.1.1Recent studies41§6.1.2PA classification42§6.1.3Architecture choice42§6.2A little piece of theory44§6.2.1Efficiency definitions44§6.2.2Class-A power amplifier44§6.2.3Loadline theory46§6.3Design approach for the PA46§6.3.1Design approach for the output stage46§6.3.2Design approach for the interstage matching49§6.3.3Design approach for the input49§6.3.4Stability50§6.3.5PA schematics with component values50§6.4Measurement approach52§6.4.1Simulation results52§6.4.2Summary of simulation results55§6.5Layout55§Bibliography57§Abbreviation and symbols61§Conceptual formulation63§Curriculum vitae65